During a read operation that reads data from a cell of a memory device (“a cell data read operation”), a word line corresponding to the cell is activated to turn on a transistor in the cell. The data stored in the cell is delivered via the turned-on cell transistor to a bit line. Since the capacitance of the bit line is greater than the capacitance of the cell, the voltage variation on the bit line may be small. This small voltage variation is sensed and amplified by a bit line sense amplifier, and then delivered to a local data line. The data path of a write operation may be the opposite of the above-described data path for the read operation.
FIGS. 1A and 1B are timing diagrams that illustrates certain timing parameters associated with a conventional memory cell data read operation. In FIG. 1A, the read operation involves a single column cycle (i.e., a column cycle of 1).
Referring to FIG. 1A, the cell data read operation starts when the voltage on the word line is activated by, for example, raising the voltage from VSS to VPP. As shown in FIG. 1A, the activation of the word line may cause a relatively small voltage variation on the bit line. Then, a bit line sense amplifier may sense this small change in the bit line voltage and amplify it. Thus, the cell data that corresponds to an input column address is amplified to the amplified voltage on the bit line, and this amplified voltage is transmitted to a local data line that corresponds to the column address. Thereafter, the voltage of the word line drops back to VSS (i.e., the word line is turned off). The bit line, however, is maintained at an elevated voltage. Thereafter, in preparation for a subsequent read or write operation, an equalizing operation is performed in which the bit line BL and the complimentary bit line BLB are electrically shorted to precharge the bit line BL and the complimentary bit line BLB to VBL.
As shown in FIG. 1A, the time interval from the time at which the word line starts to turn off until the time at which the operation to equalize the bit lines starts is designated as ta1. The time at which the word line starts to turn off is referred to herein as the “word line off time” and the time at which the bit line equalization operation starts is referred to herein as the “bit line equalization start time.” As is also shown in FIG. 1A, the time interval between the bit line equalization start time through the termination of the bit line precharge operation is designated as tb1. The time interval between the end of the precharge operation through the time at which the word line might be reactivated in the next subsequent read or write operation is designated as tc1. The time interval tc1 represents the timing margin between the termination of the precharge operation and the start of the next read or write operation. Finally, as is also shown in FIG. 1A, the time interval between the activation of the word line and the activation of the next word line in the case of a column cycle of 1 is designated as tRCmin.
FIG. 1B is a timing diagram illustrating the timing of a conventional cell data read operation in a case where the number of column cycles is 2. As shown in FIG. 1B, the process of sensing and amplifying data on the bit line in response to activation of the word line may follow the same process described above with respect to FIG. 1A, and hence this part of the process will not be re-described here. However, as the number of column cycles is 2, the access to the cell data is performed twice. Accordingly, in the example of FIG. 1B, the time interval between activation of the word line and activation of the next word line is tRCmin+2tCK.
In the example of FIG. 1B, the bit line sense amplifier operates for two access operations of the column address since the number of column cycles is 2. In this case (and in the case where the number of column cycles exceeds 2), the voltage of the bit line may be saturated to VDD or VSS. As shown in FIG. 1B, the time ta2 may be the same as time ta1 of FIG. 1A. However, as the bit line BL and the complimentary bit line BLB are equalized from a saturated state, the time interval tb2 may be increased as compared to tb1 of FIG. 1A.
Therefore, the timing margin tc2 of FIG. 1B may be decreased compared with the timing margin tc1 of FIG. 1A, thereby deteriorating operation characteristics in the high speed memory devices.